The present invention relates to a signal receiving and signal processing unit. The invention relates more specifically to a signal receiving circuit and a signal processing circuit where the character of the signals are in the form of pulse-shaped voltage variations having a selected high repetition frequency, such as from the megabit per second (Mb/s) area up to the gigabit per second (Gb/s) area, more than 1 Mb/s and preferably more than 100 Mb/s.
The voltage variations are controlled to represent a digital information-carrying signal, with an internal structure, by a transmitting circuit. The digital signal is distorted by, among other things, the signal transferring conductor. The receiving circuit is intended to be able to detect and receive a thus distorted digital signal.
Units of this kind are used to adapt received (distorted) signals into transmitted signals having an internal signal structure. A received signal which presents a somewhat erroneous voltage level and/or is not adapted to a certain common mode (CM) area is to be adapted, by the signal processing unit, to an internal signal structure more suitable to the requirements that are needed in an exchange of signals.
Such signal receiving and signal processing units are connected to a conductor adapted to transmit information-carrying signals in the form of voltage pulses. The conductor is connected to a transistor, belonging to a signal receiving circuit, to have an effect upon a current by using variations in the voltage pulses and the voltage value of a pulse. The current is in the form of pulses that are passing through the transistor, and the current is generated by voltage pulse variations and a voltage level. In the signal processing circuit, the current is adapted to an information-carrying form better suited to the internal circuit structure than the received signal was.
Signal receiving and signal processing units of this kind have been useful to evaluate the information content in voltage pulses having pulse rates in the range of up to 200 Mb/s. These units have been adapted to be able to detect pulse-shaped voltage variations appearing on a single conductor (single-ended signalling), or appearing on or between two conductors (differential signalling). The following description will, in the interest of simplicity, be limited to the application where differential signalling is used, even though the invention is applicable to both types of signalling systems.
It is obvious to one skilled in the art what measures are to be taken to keep the voltage potential of one conductor at a constant level, which is required at single ended signalling. This will, nevertheless, be described in the following.
It is known to use various techniques to manufacture these signal receiving and signal processing units to thereby achieve various working conditions. Both CMOS technology and bipolar technology have been used to manufacture signal receiving units and signal processing units of the aforementioned kind. The following description will mainly describe CMOS technology, as the differences in function due to the use of bipolar technology are of minor significance and are obvious to one skilled in the art. It is further obvious to one skilled in the art what changes are required to adapt CMOS technology and/or bipolar technology to other known technologies.
When manufacturing units of this kind there are, among other things, the following criteria that are of significant importance.
A. The span and voltage values of the CM area pertaining to the signal receiving circuit and the signal processing circuit. (The CM area is the voltage area that the received voltage pulses are to be within to be detected by the signal receiving circuit, in a differential transmitting system.) PA1 B. The limiting value of the repetition frequency, which is the highest frequency of the voltage variations on the conductors that can be detected and distinguished from each other by the signal receiving circuit and thereafter processed by the signal processing circuit. PA1 C. The voltage variations or amplitude variations that are required to detect the signals, where small amplitudes can be accepted at low rates, but at higher rates greater amplitudes are required.
It is known to connect the information-carrying signals that appear on the conductors to the gate connections belonging to PMOS transistors, where the CM area comprises the voltage area from somewhat above half of the supply voltage (Vcc) down to zero potential. The use of a PMOS transistor and a post-connected current mirror or a post-connected cascode connection likewise provides a downward extending CM area, to somewhat below zero potential (approximately -0.7 V).
It is also known that PMOS transistors present a lower limiting value, of the repetition frequency (up to 200 Mb/s) than that provided by NMOS transistors. Using NMOS transistors instead of PMOS transistors would provide a CM area extending from the supply voltage down to somewhat below half the supply voltage. This is not acceptable since, in a practical application, the CM area has to be at least within the area that is provided with PMOS transistors and a post-connected current mirror or a cascode connection.
When constructing signal receiving and signal processing units of aforementioned kind, it is known to use and coordinate two transistors within the signal processing circuit so that a current passing through a first transistor is mirrored to be the same through a second transistor, and the drain-source voltage of the second transistor can be permitted to vary relatively greatly in relation to the current variation through the first transistor.
It is also previously known to make the current through the second transistor further independent of the drain-source voltage (a high impedance current generator) by means of a cascode connection. Other current mirror connections are also known, such as a connection having three transistors known as the "Wilson Current Mirror". Reference is made to the publication, P. E. Allen, CMOS Analogue Circuit Design (ISBN 0-03-006587-9) to provide a further and more detailed understanding of the earlier known prior art.
CMOS technology uses PMOS transistors and NMOS transistors, and in the following, transistors will be described with an "N" or a "P" before their reference numerals to indicate whether the transistor is an NMOS or a PMOS transistor, respectively. The expression "current mirror" will in the following description and claims be understood to cover every kind of current minor regardless of whether two, three, or more transistors are used. The Wilson circuit and the cascode circuit represent current mirror connections that provide better attributes when connected as current generators.
While the following description uses the term "NMOS transistors", this term should be considered to include bipolar NPN transistors and equivalent transistors of other technologies. Bipolar PNP transistors and the like are also to be included in the term "PMOS transistors".
It is further known that selected current values through a signal receiving transistor are, within a certain area, in direct proportion to the ability to receive, detect, and process signals of a higher rate. The upper limit of the current value is set to where the transistor leaves or goes out of the amplifying mode because of the current density within the transistor.
The present invention can further be regarded as a further development of the signal receiving and signal processing unit that is described in more detail in Swedish Patent Application No. 9400593-1, filed Feb.21, 1994, and corresponding U.S. Patent Application No. 08/391,005, filed Feb. 21, 1995, which is now U.S. Pat. No. 5,568,082 that is incorporated here by reference.